LWWRegister

A last-writer-wins register. Each set tags the value with (timestamp, replicaId); piece picks the entry with the largest tag, breaking ties on replicaId lexicographically so the merge is deterministic regardless of arrival order.

Wall-clock or causal time? This register treats whichever monotonically- increasing source the caller passes as timestamp as the truth — wall-clock is the common case but skew can silently drop a value. NTP-class drift will cause surprising silent drops: a write with a lagging timestamp loses to an older write from a faster clock. For semantics that preserve concurrent writes use MVRegister; for correctness under arbitrary clock skew, pair with a Hybrid Logical Clock above this layer.

Samples

val a = ReplicaId("A")
val b = ReplicaId("B")

val left = LWWRegister.empty<String>().set(a, timestamp = 1L, value = "v1")
val right = LWWRegister.empty<String>().set(b, timestamp = 2L, value = "v2")

check(left.piece(right).value == "v2")  // ts=2 wins
check(right.piece(left).value == "v2")  // commutative